1. Technical Field
The embodiments described herein relate to a data strobe signal generating device, and more particularly, to a data strobe signal generating device and a semiconductor memory apparatus is using the same.
2. Related Art
In general, a synchronous semiconductor memory apparatus, such as a double data rate synchronous dynamic random access memory (DDR SDRAM), uses a data strobe signal ‘DQS’ serving as a reference for a data strobing time point. The data strobe signal ‘DQS’ has a preamble, which represents the start of a read or write operation of a semiconductor memory apparatus, and a postamble that represents the end of the read or write operation. If the preamble and the postamble of the data strobe signal ‘DQS’ are not normally generated, a signal may not be normally exchanged between a controller and the semiconductor memory apparatus.
FIG. 1 is a schematic block diagram of a conventional data strobe signal generating device. In FIG. 1, the data strobe signal generating device 1 includes an enable signal generator 10, a preamble pulse generator 20, and a data strobe signal output unit 30.
The enable signal generator 10 receives first and second output enable signals ‘OE1’ and ‘OE2’ to generate an enable signal ‘QSENPRE’. The first output enable signal ‘OE1’ is enabled prior to a CAS latency by a 1.5 clock signal and the second output enable signal ‘OE2’ is enabled prior to the CAS latency by a 0.5 clock signal. Thus, the enable signal ‘QSENPRE’ is enabled for one period of a clock signal.
The data strobe signal output unit 30 receives the enable signal ‘QSENPRE’ and a delay locked loop (DLL) clock signal ‘dll_clk’ to generate a preamble signal ‘QSPRECLK’. The data strobe signal output unit 30 receives the preamble signal ‘QSPRECLK’ to generate a data strobe signal ‘DQS’.
FIG. 2 is a schematic circuit diagram a conventional data strobe signal output unit of FIG. 1. In FIG. 2, the data strobe signal output unit 30 includes first and second PMOS transistors P1 and P2, a first NMOS transistor N1, and first to third inverters IV1 to IV3. The data strobe signal output unit 30 enables a down-signal ‘dn’ in response to the preamble signal ‘QSPRECLK’, thereby generating a preamble of the data strobe signal ‘DQS’.
FIG. 3 is a timing chart of a conventional data strobe signal generating device of FIG. 1. In FIG. 3, the enable signal generator 10 receives the first and second output enable signals ‘OE1’ and ‘OE2’ to generate the enable signal ‘QSENPRE’ having an enable interval corresponding to one period of a clock signal.
The preamble pulse generator 20 (in FIG. 1) generates the preamble signal ‘QSPRECLK’ enabled at a low level by a pulse width of the DLL clock signal ‘dll_clk’ input in an interval in which the enable signal ‘QSENPRE’ is enabled.
The data strobe signal output unit 30 receives the preamble signal ‘QSPRECLK’ at the low level to generate the down-signal ‘dn’ enabled at a high level, thereby generating the preamble of the data strobe signal ‘DQS’.
However, in a semiconductor memory apparatus, the enable signal ‘QSENPRE’ may not be enabled at normal timing due to process, voltage, temperature (PVT) variations or layout loading.
FIG. 4 is a schematic block diagram of a conventional data strobe signal generating device including a layout loading. In FIG. 4, high loading exists in a circuit until the enable signal ‘QSENPRE’ is input to the preamble pulse generator 20 after the enable signal ‘QSENPRE’ is generated from the enable signal generator 10. Here, the layout loading 40 is shown.
FIG. 5 is a timing chart of a conventional operation of the data strobe signal generating device of FIG. 4. In FIG. 5, the enable signal ‘QSENPRE’ is enabled after being delayed from the original enable time point due to the layout loading 40 (in FIG. 4). In such a case, since the enable signal ‘QSENPRE’ does not sufficiently cover the DLL clock signal ‘dll_clk’, the preamble pulse generator 20 (in FIG. 4) generates the preamble signal ‘QSPRECLK’ having a narrower pulse width, so that the preamble of the data strobe signal ‘DQS’ may not be normally generated. Accordingly, the semiconductor memory apparatus will not function properly.